This invention relates to high-speed current switching circuitry and, more particularly, to a current switching tree having cascaded sets of switching circuits with an input set being driven at a constant, fixed sampling rate and with means for reducing the effective sampling frequency of the tree while maintaining said constant, fixed sampling rate.
As described in the aforementioned specification, a high-speed current sampling circuit is formed as a switching tree comprised of successive, cascaded sets of switching circuits, with each succeeding set being supplied with sampling pulses of reduced frequency. This switching tree permits the sampling at a satisfactorily high rate of an input signal having high frequency components, while enabling each sample which is produced at the aforementioned high rate to be processed at a relatively lower speed. Thus, current samples can be produced on the order of about 1 GHz; but each such sample may be stored temporarily and then digitized at a relatively low rate well within the operating capabilities of inexpensive analog-to-digital (A/D) converters.
Accurate operation of such high-speed switching circuits is dependent, to a large degree, upon the stability of the clock generator used to produce the sampling pulses supplied to the respective sets in the switching tree. Typically, a crystal oscillator is used as a reference clock source because it exhibits a fixed, stable frequency at high repetition rates. Usually, circuit components are selected on the basis of their ability to switch quickly and accurately, without saturation and without being susceptible to drift, delays and phase shifts at high operating speeds. Good circuit design thus takes into account various capacitive components of the circuits being used. While the fabrication of such circuits as an integrated circuit minimizes deleterious influences at high operating speeds, optimum circuit design nevertheless is premised upon a particular operating rate at which the switching tree is driven.
Accordingly, it has been found that it is not an easy matter to operate an expensive, high-speed switching tree at low speeds because of the design considerations upon which the circuit design was based. That is, less than optimum performance is attained if the crystal oscillator normally used to supply sampling pulses to the switching tree is replaced by an oscillator exhibiting a lower repetition rate. Likewise, a switching tree designed for high operating speeds may not operate satisfactorily if the normally high repetition rate of the clock signals generated by the aforementioned crystal oscillator is divided by conventional frequency dividers, programmable dividers, or the like.
Although separate switching trees may be purchased for use at respectively different frequencies, with each tree being designed to operate at a respective one of those frequencies, the stockpiling of several switching trees, each for use at a separate operating speed, is redundant and expensive. Hence, there has been a need to provide a switching tree operable at various different effective sampling rates without sacrificing performance or operating characteristics regardless of the operating speed at which the sampling tree is used.
To increase the sampling speed of the aforementioned switching tree, it has been proposed to supply an input signal to be sampled to plural phases of switching trees, each operable at the same sampling rate but at respectively different phases. For example, if three phases of sampling trees are used, with the input set of each phase being driven at a sampling rate of f.sub.s, an input signal supplied to these three phases is sampled at an effective sampling frequency of 3f.sub.s. It is important, however, particularly if the input signal exhibits very high frequency components, such as transients, that the respective phases of the sampling clock pulses supplied to these switching trees be maintained within strict limits. For instance, in the aforementioned example wherein three phases of switching trees are used, the sampling clock pulses should be supplied at 0.degree., 120.degree. and 240.degree. to these respective phases. It is difficult, however, to provide fine phase adjustments at the very high sampling frequencies exhibited by the sampling clock pulses.